WLCSP (Wafer level chip scale package) High Power Burn-in KYEC Bio Chip Testing

At present, KYEC has provided many advanced technology services of wafer level chip scale package (WLCSP) and testing to large international semiconductor manufacturers. We use a Pogo Pin probe card to contact the wafers for WLCSP testing. For the WLCSP components testing, the height difference between different testing sites may be as high as 200 μm. The Pogo Pin design can overcome the variation of the WLCSP package height. At the same time we have successfully developed a solution for testing 128 sites at the same time, which can improve test efficiency and increase outputs.

In the future, WLCSP's packaging and testing services will become more and more important with the development of electronic components' multiple functions and high density. KYEC will never be absent in this important technology development competition.


WLCSP Testing Achievement

  • 128 sites parallel testing is successful
  • Pogo pin probe card, printed circuit board (PCB) and interface are all developed by KYEC
  • Improving efficiencies of 128 sites parallel testing


The specifications of the Pogo Pin probe card designed by KYEC for WLCSP are as follows:



Bump pitch

500 μm

Probe area

45 mm x 30 mm

Tip co-planarity

± 20 μm

Temperature range

-40℃ ~ 120 ℃

Contact site

128 Site

Solder ball diameter

250 μm

XY accuracy

± 50 μm

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