Design-to-Test Solutions Provider.KYEC's capability includes complete...
KYEC has developed Vertical P/C, the mass production of which is ongoing. This advanced technology has an edge over the mainstream products on the market in terms of fine pitch and pin count and exhibits excellent performance. Vertical P/C can overcome disadvantages of conventional cantilever probe cards. For example, the pins can easily be scorched because of low ability to withstand current, and a high pin count is likely to negatively affect testing stability.
KYEC has the capacity to develop and manufacture Vertical P/C independently. Therefore, compared with the current industry-standard costs of producing Vertical P/C, our Vertical P/C is considerably less expensive. Thus, our clients can assume an unmatchable advantage in test costs and production efficiency.
Currently, the method used in high-frequency Mobile SoC packaging is the copper pillar method. Consequently, bump devices are the major technologies used in CP testing over the recent years. The advantages of Vertical P/C are thus highlighted. In particular, Vertical P/C exhibits superior performance, can be maintained and repaired rapidly, and decreases testing difficulty when used in products featuring high pin count or high current. For example, site unbalance and crosstalk can be used to test high-speed signals.